The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Nonetheless, it has been found that from 0.13 μm and bellow, the layout of an electronic design exhibits profound impacts on device electrical parameters, especially in sub-45 nm nodes. For example, stress effects caused by the length of oxide (LOD) definition or shallow trench isolation (STI) features impact the mobility (μeff), carrier saturation velocity (Vsat), or threshold voltage (Vth) of metal-oxide-semiconductor (MOS) transistors. Well-proximity effect (WPE) also cause significant variation in the threshold voltages depending on the proximity of CMOS (complementary metal-oxide-semiconductor) transistors to an implant well boundary.
In addition, a typical design flow often uses various design rules and layout guidelines such as dummy components in module, well creation guidelines, device matching guidelines, etc. to minimize such layout dependent effects by verifying the physical design during sign-off via extraction and re-simulation through multiple iterations. If such verification fails, the design process reverts back to the layout or even back to the schematic design stage and repeats the schematic, layout, and verification process flow iteratively in order to meet a final layout with acceptable performance or manufacturing criteria.
Module creation constitutes a critical part of analog or analog and mixed signal design flows. In a typical module creation design flow, a schematic designer creates or combines multiple instances of one or more components, devices, nets, or parts of one or more nets (hereinafter “component”) into a more complex, matched, and structured module. The schematic designer may, for example, specify how the one or more components are to be arranged, an interdigitation pattern, what and how one or more dummy devices are to be arranged, body contacts, or guard rings for the module. Once the schematic designer sets up how the module is to be created, the schematic designer may hand off these parameters to a layout designer who in turn use a module generation tool, a module compilation tool, or a module creation too (collectively “module creation tool”) to create the physical module in a physical layout. The physical layout is then extracted, simulated, and verified to determine whether the physical layout meets circuit performance specifications.
Nonetheless, in technologies at process nodes 45 nm and below, the device placement and routing within these modules may significantly impact the performance or reliability of the electronic circuits. For example, insufficient wire widths within the physical module or a part of the entire layout associated with the physical module may lead to electro-migration violations that may negatively impact the reliability or performance of the electronic circuits.
Thus, there exists a need for implementing analysis-driven module creation and for implementing electrically aware simulation for an electronic design.